Burst-Mode Clock Recovery Circuit with a Novel Dual Bit-Rate Structure in 0.n1 8-m CMOS

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gatedII. GATED-OSCILLATOR BASED CLOCK RECOVERY oscillators to align clock with data edges and can operate in GOCRC (Gated-Oscillator based Clock Recovery half-rate clocking mode, doubling data throughput, as well as Circuit) was originally developed for magnetic drum data in full-rate clocking mode. The gated-oscillator reset-phase storage application in 1954 [7]. It is used for burst-mode control scheme alters the starting phase of gated-oscillators receivers because of its instantaneous locking property. It is repeatedly between 00 and 1800 according to the current clock popular also in multi-channel receivers in which many phase. A prototype chip was designed with 0.18-. m CMOS receivers should be integrated on a single chip [8], because it technology and 1.25/2.5-Gb/s dual-mode operation was verified takes small chip area and consumes low power. in measurement. Fig. 1 shows a schematic diagram of a gated-oscillator. A back-to-back connected delay stage chain and a gate stage